1. Field
The present invention resides in the field of semiconductor devices and processes for their production. In particular, the invention is directed toward the electrical isolation of semiconductor devices in a semiconductor substrate.
2. Prior Art
Typically, integrated circuits are fabricated as multiplicity of interconnected devices such as diodes, transistors and the like, within a monolithic body of semiconductor material. It is essential that the devices may be fabricated side-by-side within the substrate, and yet without the occurrence of any undesired interaction therebetween. To prevent unwanted interaction it is common practice to provide some form of electrical isolation barrier between the devices. Usually, the isolation is achieved by providing a diffused region between the devices as a PN junction which is readily reverse-biased to preclude current flow across the junction.
The prior art PN junction isolation technique has proved successful, but it has the distinct disadvantage of severely limiting the surface area of the semiconductor body (e.g., chip, slice, etc.) available for device fabrication. Specifically, as the isolation region diffuses into the semi-conductor body in a direction perpendicular to the surface it also spreads laterally (i.e., parallel to the surface) toward the devices which are to be isolated. In the case of transistor isolation, the diffused region must not come into actual contact with either transistor because that can lower the breakdown voltages and short circuit the bases. Accordingly, it is essential, where PN junction isolation is used, that sufficient space be provided between the devices to account for diffusion and depletion layer spreading. This space between devices is wasted area because it is useless for any other purpose.
Another prior art device isolation technique involves the deposition of a silicon nitride film on the semiconductor surface, the etching of grooves through the film and into the semiconductor body, followed by thermal growth of silicon dioxide to fill the grooves. The nitride retards the growth of the oxide other than in the grooves and is subsequently etched away to leave oxide isolated semiconductor islands with a planar surface. The technique has been dubbed "isoplanar". It suffers the disadvantage of being useful for only relatively shallow moats (e.g., about 1 micron) and hence limits the depth of isolation and of the island, thereby limiting the type of device which may be fabricated in the island. There is a critical time limitation on oxide growth before the nitride begins to break down and before any buried layer begins significant diffusion toward the planar surface, in subsequent processing. Further, the oxide thickness is limited by the magnitude of the temperature to which it must be subjected during subsequent processing.